|Course Title||Computer Organisation and Assembly
|Last Dates for Submission||15th October 2019 (For July 2019 Session)
15th April 2020 (For January 2020 Session)
There are four questions in this assignment, which carries 80 marks. Rest 20 marks are for viva voce. You may use illustrations and diagrams to enhance the explanations. Please go through the guidelines regarding assignments given in the Programme Guide for the format of presentation. Answer to each part of the question should be confined to about 300 words. Make a suitable assumption, if any.
Q1. (Covers Block 1)
(a) Please refer to Figure 4 of Unit 1 of Block 1 on page 11. Assuming the same machine to be used for the execution of the following three consecutive instructions:
LOAD C; Loads the content of Memory location C into the Accumulator Register.
ADD B; Adds the content of memory location B in the Accumulator Register.
STORE A; Stores the content of Accumulator register AC in memory location A.
The following are the details about the instructions, data and registers:
- Each word of memory is of 32 bits in length. Each instruction is also 32 bits long.
- Main Memory has 256 words.
- The three consecutive instructions, as shown above, starts from memory location (1F)h; A is at location (FD)h and contains a value (1000)h, B is at location (FE)h and contains a value (FF3B)h and C is at location (FF)h and contains a value (2A2F)h.
- The AC, IR and MBR registers are of size 32 bits, whereas PC and MAR registers are of size 8 bits. The initial content of PC register is (1F)h
Draw the diagrams showing addresses and content of memory locations and Registers. Show how the content of memory locations and registers will change with the execution of the three instructions. Show all the addresses and values in hexadecimal notations. You must also perform the necessary arithmetic using signed 2’s complement notation and show the results indicating overflow if any. Also, explain the process of execution of the instructions. (4)
(b) Perform the following conversion of numbers: (2)
i) Decimal (3412454512)10 to binary and hexadecimal
ii) Hexadecimal (FEDCBA9)h into Octal.
iii) String “in file name % mean blank.” into UTF 8.
iv) Octal (7766432) O into Decimal
(c) Assuming that inverse is represented as ‘, simplify the following Boolean functions:
F= ((A’ + B)’ + (A’+B’)’)’ (1)
(d) Simplify the following function using K-map:F(ABCD)=∑(0, 2, 6, 8, 10, 14)
Draw the circuit using NAND gates. (2)
(e) Consider the Adder-Subtractor circuit as shown in Figure 3.15 page 76 of Block 1. Explain how this circuit will perform subtraction if the value of A is 1111 and B is 1100. You must list all the bit values including Cin and Cout and overflow condition. (1)
(f) Explain the functioning of a 2× 1 Multiplexer. You must draw its truth table and explain its logic diagram with the help of an example input. (2)
(g) Assume that a data value 1111 was received as 1011. Explain how use of Hamming’s Error-Correcting code will send this data value from source and correct error at the destination. (2)
(h) Explain functioning of S-R flip flop with the help of logic diagram, characteristic table and excitation table. (2)
(i) Explain the functioning of Asynchronous and Synchronous counter. Explain how they are different from each other. (2)
(j) Differentiate between fixed point numbers and floating point numbers? Explain the representation for Zero in IEEE 754 single precision standard. Represent (-32.25)10 and (0.000125)10 in IEEE 754 single precision format. (2)
Q2. (Covers Block 2)
(a) Reference Figure 2(b) on page 8 in Unit 1 of Block 2. Draw the Internal organisation of a 64×8 RAM. Also answer the following:
(i) How many data input and data output lines does this RAM needs? Explain your answer.
(ii)How many address lines are needed for this RAM? Give reason in support of your answer. (2)
(b) A computer has 16 MB RAM and has a word size of 32 bits. It has cache memory having 16 blocks having a block size of 64 bits. Show how the main memory address (17F0AB)h will be mapped to cache address, if
(i) Direct cache mapping is used
(ii) Associative cache mapping is used
(iii)Two way set associative cache mapping is used.
You must clearly identify tag, index, main memory block address and offset etc. in your answer. (3)
(c) Explain the process of Interrupt handling and Return from interrupt with the help of a diagram. You must answer this question in your own words. (2)
(d) Differentiate between the working of DMA and I/O processor. Explain the DMA configurations and I/O channel structures. (3)
(e) Assume that a disk has 2000 tracks with each track having 256 sectors and each sector is of size 2M. A file having the name openUni.txt is of size 32 M. Assume that disk has 16 free – continuous clusters of 4 sectors each at different locations on the disk. How can this file be allotted space on the disk? Also show the content of FAT after the space allocation to this file. You may make suitable assumptions. You may assume the cluster size as 4 sectors, if needed. (4)
(f) Explain the following giving their uses and advantages/disadvantages. (Word limit for answer of each part is 50 words ONLY) (6)
(i) SCSI and IDE in the context of Interfaces
(ii) Scanner and its resolution
(iii) Scan codes in the context of keyboard
(iv) Access time on disks
(v) Virtual Memory
(vi) RAID level 0, 3 and 5
Q3. (Covers Block 3)
(a) A computer has a single-core processor having 16 General purpose registers and 4 additional special-purpose registers. The machine has 1MB RAM. The size of each register and memory word is 32 bits each. An instruction of the machine is of fixed length and is equal to one memory words. Each instruction of the machine can have two operands one memory operand and second register operand (register operand can be in General purpose registers only). Memory operand either uses direct addressing or is an immediate operand; however, register operand can use either register direct or register indirect addressing. (Please note that if register operand uses indirect addressing, then stated register contains the address of the operand in the memory.) An instruction of a machine consists of operation code bits, two addressing mode bit, one register operand and one memory operand. The addressing mode bits specify addressing mode as:
|Addressing mode bit||Register Operand||Memory Operand|
The special-purpose registers are – Program Counter (PC), Memory Address Register (MAR), Data Register (DR) and Flag registers (FR). The first register of the General purpose registers can be used as Accumulator Register. The size of Integer operands on the machine is 32 bits and it may be assumed to be equal to the size of accumulator register. In order to execute instructions, the machine has an additional Instruction Register (IR) of size 32 bits as each instruction is of this size. Perform the following tasks for the machine.
(i) Design suitable instruction formats for the machine. Specify the size of different fields that are needed in the instruction format. Also indicate how many different operations can be coded for this machine. Give reasons in support of your answer.(3)
Put some valid values in registers and memory locations and demonstrate examples of different addressing modes of this machine. (1)
(iii) Assuming that the instructions are first fetched to Instruction Register (IR) and memory operands is brought to DR register; indirect operand is brought to Accumulator register; and result of operation is stored in the Accumulator register; write and explain the sequence of micro-operations that are required for fetch and execute cycles of an instruction which performs subtraction of two operands having addressing mode bits as 00. Please note that one of the operand is Indirect Register Operand and the second is a direct memory operand. Make and state suitable assumptions, if any. (6)
(b) Assume that you have a machine as shown in section 3.2.2 of Block 3 having the micro-operations as given in Figure 10 on page 62 of Block 3. Consider that R1 and R2 both are 8 bit registers and contains 11000011 and 11100101 respectively. What will be the values of select inputs, carry-in input and result of the operation (including carry out bit) if the following micro-operations are performed? (For each micro-operation you may assume the initial value of R1 and R2 as given above) (2)
(i) Add R1 and R2 with carry
(ii) Decrement R1
(iii)Shift right R1 twice
(iv) AND R1 and R2
(c) What is the role of Control Signal in the execution of an Instruction? Block 3, page number 68-70, explains the timing sequence for execution of ISZ instruction. Explain the execution of an ADDITION instruction with the help of micro-operations and timing sequence. (3)
(d) What is the role of micro-programmed control Unit? How a micro-program is executed? Explain with the help of a diagram. (2)
(e) List and explain the characteristics of RISC machines. A RISC machine has 256 registers out of which 64 registers are reserved for the Global variables and 64 for Instruction related tasks. This machine has been designed to have 12 registers for storing three input parameters, three output parameters and six local variables for a function call. Explain with the help of a diagram, how the overlapped register window can be implemented in this machine for function/procedure calls. You must explain how the parameters will be passed when a function calls another function. How many levels of procedural calls, such a machine can support?
Q4. (Covers Block 4)
(a) Write a program using 8086 assembly Language (with proper comments) that accepts an input of ten characters from the keyboard and store them in the memory. It then converts all the lower case alphabets of this stored string to uppercase alphabets. Make suitable assumptions, if any. (7)
(b) Write a program using 8086 assembly Language (with proper comments) that finds the sum and average of 10-byte numbers stored in two different arrays of size 5 each. (7)
(c) Explain the following in the context of 8086 Microprocessor (6)
(i) Use of Segment Registers
(ii) Use of Interrupts in Input/output
(iii).com and .exe programs